Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a Mixed-Signal IC Layout Design Engineer to own a full‑custom layout for high‑performance analog and mixed‑signal IP in advanced FinFET nodes. You'll translate schematics into manufacturable layouts that hit aggressive performance, power, area, and reliability targets, and integrate these blocks cleanly into larger SoCs.
This role is remote, based out of North America.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
Who You Are
An experienced analog/mixed‑signal IC layout engineer with 5 years experience delivered silicon in CMOS/FinFET nodes. Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments, including constraint‑driven layout and PCells.
Strong understanding of CMOS devices, interconnect stacks, and advanced‑node rules, including multi‑patterning, density/fill, and lithography‑driven constraint
